Power supply noise (also sometimes called simultaneous switching noise) may occur in a semiconductor integrated circuit, such as a large scale integrated circuit (LSI) when there is a significant change in computational load or the number of circuits running amongst a plurality of circuits included in the semiconductor integrated circuit. When power supply noise has occurred, a power supply voltage drop may lead to insufficient voltage supply to the circuits in the semiconductor integrated circuit. This could increase the propagation delay time (hereinafter referred to simply as delay time) of a signal propagating through the semiconductor integrated circuit, thus causing timing errors.
There are conventionally proposed adaptive clocking control (ACC) circuits used to avoid timing errors caused by power supply noise (see, for example, Japanese Laid-open Patent Publication No. 2017-17671). Such an ACC circuit monitors the power supply voltage to detect a drop in the power supply voltage, using a power supply noise monitor. If the power supply voltage falls at or below a predetermined threshold, the ACC circuit reduces the frequency of a clock signal supplied to circuits in a semiconductor integrated circuit, to thereby avoid timing errors. In the case of using no ACC circuit, the clock frequency is determined in consideration of timing errors occurring when power supply noise generated inside the semiconductor integrated circuit reaches its maximum; however, such a determination need not be made when the ACC circuit is used.
Some power supply noise monitors used in ACC circuits take advantage of the change in signal delay time resulting from power supply noise. Critical path monitors (CPM) are one example of such power supply noise monitors. A CPM includes, for example, a delay circuit with a delay time equal to that of a path in a semiconductor integrated circuit, with the largest delay (such a path is called a critical path). In order to output a value representing the magnitude of power supply noise, the CPM takes advantage of the setup margin of a flip-flop to which a signal is transmitted, being reduced due to an increased delay time of the delay circuit caused by a drop in the power supply voltage.
There are conventionally proposed techniques for correcting, according to temperature, the frequency of a clock signal output from a temperature-dependent oscillator (see, for example, Japanese Laid-open Patent Publication No. 2007-312194). There are also conventionally known techniques for keeping a gate delay time constant by preliminarily tabulating results of measuring change characteristics of the gate delay time in relation to temperature and power supply voltage and then changing the power supply voltage based on the prepared table and a device temperature (see, for example, Japanese Laid-open Patent Publication No. 08-265118).
As for power supply noise monitors using the change in delay time resulting from power supply noise, the delay time is also affected by temperature. Therefore, in the case of controlling the frequency of a clock signal using such a power supply noise monitor, there remains a problem that temperature dependence of the delay time reduces accuracy in controlling the frequency of the clock signal.